Typically, first-in-first-out register arrays (“FIFOs”) have been used to store and transmit data. When storing and transferring data within a same clock domain, i.e., rate of data transfer, a synchronous FIFO is used. In contrast, when storing and transferring data between two clock domains, an asynchronous FIFO is used. In particular, an asynchronous FIFO allows for the storage and extraction of data while converting the data from a first clock domain to a second clock domain. Control circuitry containing flip-flops, pointers, double-sync logic, gray code conversion tables, etc. is used to control the traversal of the data through the FIFOs.
When large amounts of data are to be stored and transmitted through multiple clock domains, a large asynchronous FIFO and corresponding control circuitry are necessary. For an asynchronous FIFO of size 2N bits, N-bit sized pointers are necessary for the operation of the FIFO. For example, if an asynchronous FIFO is of size 212 bits, the pointers and logic tables contained within the control circuitry can be as large as 12 bits each. This amounts to a large amount of space required for the control circuitry. Also, the amount of time required to implement such a large asynchronous FIFO is increased due to the large double-sync logic and gray code tables. For example, to determine whether the asynchronous FIFO is full, the control circuitry must traverse the entire asynchronous FIFO and cross multiple clock domains.